3DEP: A Efficient Routing Algorithm to Evenly Distribute Traffic Over 3D Network-on-Chips

• Published in: Proceedings - Euromicro Workshop on Parallel and Distributed Processing pp. 237 - 241
• Main Authors: Vahdatpanah, Fatemeh, Elahi, Mahdi, Kashi, Somayeh, Taheri, Ebadollah, Patooghy, Ahmad
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2019
• Subjects: 3D Network-on-Chip; Deadlock; Elevators; Partially Adaptive; Routing; Routing Algorithm; Simulation; System recovery; Three-dimensional displays; Through-silicon vias; Throughput; Turn Model
• ISSN: 2377-5750
• DOI: 10.1109/EMPDP.2019.8671643

Due to high manufacturing cost of Through Silicon Via (TSV) in 3D Network-on-Chips (NoCs), not every router is vertically connected. In most 3D NoCs only a subset of TSVs are contrived which results into incomplete 3D NoCs in the vertical dimension. This irregularity introduces new complexity in the design of efficient routing algorithms for partially connected 3D NoCs. In this paper, we propose an efficient routing algorithm to evenly distribute traffic in incomplete 3D NoCs. The proposed algorithm uses turn model analysis to categorize layers, columns, and rows of the NoC into different groups. Then, specific turns are prohibited in each group such that the whole routing is deadlock free, livelock free, and independent of the location of TSVs over the network. By finding the best combination for prohibited turns over the network, we limited the number of required virtual channels to two virtual channel per each physical channel. Simulation results show that the proposed partially adaptive routing has improved packet latency by 32.8% in comparison with Elevator-First algorithm. The advantage of the proposed algorithm is that it shows more improvements on the packet latency and network throughput when the size of network grows.