Dynamically reconfigurable regular expression matching architecture

• Published in: 2008 International Conference on Application-Specific Systems, Architectures and Processors pp. 120 - 125
• Main Authors: Divyasree, J., Rajashekar, H., Varghese, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2008
• Subjects: Chromium; Decoding; Engines; Field programmable gate arrays; Impedance matching; Radiation detectors; Table lookup
• ISBN: 9781424418978; 1424418976
• ISSN: 1063-6862
• DOI: 10.1109/ASAP.2008.4580165

Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching architecture on reconfigurable fabric like FPGA. We present a Non-deterministic Finite Automata based implementation with extended regular expression syntax set compared to previous approaches. We also describe a dynamically reconfigurable generic block that implements the supported regular expression syntax. This enables formation of the regular expression hardware by a simple cascade of generic blocks as well as a possibility for reconfiguring the generic blocks to change the regular expression being matched. Further, we have developed an HDL code generator to obtain the VHDL description of the hardware for any regular expression set. Our optimized regular expression engine achieves a throughput of 2.45 Gbps. Our dynamically reconfigurable regular expression engine achieves a throughput of 0.8 Gbps using 12 FPGA slices per generic block on Xilinx Virtex2Pro FPGA.