High-level synthesis algorithms with floorplaning for distributed/shared-register architectures

In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtain...

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Bibliographic Details
Published in2008 International Symposiium on VLSI Design, Automation and Test pp. 164 - 167
Main Authors Ohchi, A., Togawa, N., Yanagisawa, M., Ohtsuki, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2008
Subjects
Clocks
Computer architecture
Computer science
Delay
Hardware
High level synthesis
Integrated circuit interconnections
Processor scheduling
Registers
Wire
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ISBN1424416167
9781424416165
DOI10.1109/VDAT.2008.4542438

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Summary:In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.
ISBN:1424416167
9781424416165
DOI:10.1109/VDAT.2008.4542438