APA (7th ed.) Citation

Dev, M. P., Baghel, D., Pandey, B., Pattanaik, M., & Shukla, A. (2013, April). Clock gated low power sequential circuit design. 2013 IEEE Conference on Information and Communication Technologies, 440-444. https://doi.org/10.1109/CICT.2013.6558136

Chicago Style (17th ed.) Citation

Dev, Mahendra Pratap, Deepak Baghel, Bishwajeet Pandey, Manisha Pattanaik, and Anupam Shukla. "Clock Gated Low Power Sequential Circuit Design." 2013 IEEE Conference on Information and Communication Technologies Apr. 2013: 440-444. https://doi.org/10.1109/CICT.2013.6558136.

MLA (9th ed.) Citation

Dev, Mahendra Pratap, et al. "Clock Gated Low Power Sequential Circuit Design." 2013 IEEE Conference on Information and Communication Technologies, Apr. 2013, pp. 440-444, https://doi.org/10.1109/CICT.2013.6558136.