Clock gated low power sequential circuit design

• Published in: 2013 IEEE Conference on Information and Communication Technologies pp. 440 - 444
• Main Authors: Dev, Mahendra Pratap, Baghel, Deepak, Pandey, Bishwajeet, Pattanaik, Manisha, Shukla, Anupam
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2013
• Subjects: Clock Gating; Clocks; Conferences; Flip-flops; Glich Free Design; Logic gates; Low Power; Power demand; Power dissipation; Register Transfer Level; Registers; Sequential Circuit
• ISBN: 9781467357593; 1467357596
• DOI: 10.1109/CICT.2013.6558136

In this work, our focus is on study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level. Virtex-6 is 40-nm FPGA, on which we implement our circuit to re-assure power reduction in sequential circuit. Clock gating is implemented on smaller circuit called D flip-flop and on larger circuit called 16-bit register. The percentage of reduction in dynamic power especially clock power is verified for different device operating frequency. Here, we achieved 87.09%, 88.02%, 88.02%, and 88.01% clock power reduction in this work when clock period is 1ns, 0.1ns, 0.01ns and 0.001ns respectively. Design and implementation result shows that there is reduction in dynamic power especialy significant reduction in clock power We also achieved 15%, 14.22%, 14.58%, 14.57% and 14.57% dynamic power reduction when clock period is 10ns, 1ns, 0.1ns, 0.01ns, and 01ps respectively.