Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R

• Published in: ICIT 2006 : 9th International Conference on Information Technology : proceeding s : 18-21 December, 2006, Bhubaneswar, India pp. 273 - 276
• Main Authors: Kaivani, A., Alhosseini, A.Z., Gorgin, S., Fazlali, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2006
• Subjects: Application software; Circuit synthesis; CMOS logic circuits; Digital arithmetic; Encoding; Floating-point arithmetic; Hardware; Logic design; Optical computing; Quantum computing
• ISBN: 0769526357; 9780769526355
• DOI: 10.1109/ICIT.2006.78

The binary coded decimal (BCD) encoding has always dominated the decimal arithmetic algorithms and their hardware implementation. Due to importance of decimal arithmetic, the decimal format defined in IEEE 754 floating point standard has been revisited. It uses densely packed decimal (DPD) encoding to store significant part of a decimal floating point number. Furthermore in recent years reversible logic has attracted the attention of engineers for designing low power CMOS circuits, as it is not possible to realize quantum computing without reversible logic implementation. This paper derives the reversible implementation of DPD converter to and from conventional BCD format using in IEEE754R.