Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An...

Full description

Saved in:
Bibliographic Details
Published in2008 IEEE Custom Integrated Circuits Conference pp. 355 - 358
Main Authors Sakimura, N., Sugibayashi, T., Nebashi, R., Kasai, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
Circuits
Clocks
CMOS process
Energy consumption
Flip-flops
Large scale integration
Latches
Magnetic separation
Magnetic tunneling
Magnetization
Online AccessGet full text
ISBN9781424420186
1424420180
ISSN0886-5930
DOI10.1109/CICC.2008.4672095

Cover

Abstract A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chippsilas functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.
AbstractList A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chippsilas functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.
Author Nebashi, R.
Kasai, N.
Sakimura, N.
Sugibayashi, T.
Author_xml – sequence: 1
  givenname: N.
  surname: Sakimura
  fullname: Sakimura, N.
  organization: Device Platforms Labs., NEC Corp., Sagamihara
– sequence: 2
  givenname: T.
  surname: Sugibayashi
  fullname: Sugibayashi, T.
  organization: Device Platforms Labs., NEC Corp., Sagamihara
– sequence: 3
  givenname: R.
  surname: Nebashi
  fullname: Nebashi, R.
  organization: Device Platforms Labs., NEC Corp., Sagamihara
– sequence: 4
  givenname: N.
  surname: Kasai
  fullname: Kasai, N.
  organization: Device Platforms Labs., NEC Corp., Sagamihara
BookMark eNpVkM1Kw0AUhUdswbT2AcRNXmDi_M8ddxKMFqou1HWZTO5IJGZCEpS-vQW7cXU4i-_wcVZk0aceCbnirOCcuZtyW5aFYAwKZaxgTp-RjbPAlVBKMO7k-b8OZkEyBmCodpItSQaaGi2thAuymqZPdkQciIzcPqf-O3V-bjvMn_xHj3Mb8qprB1p1achjGvNp9n1TH-iQfnCkcUTMX1M5XZJl9N2Em1OuyXt1_1Y-0t3Lw7a829GWWz3TYL3SMqAXslFoj2oCOTBreBMi1MHyWgWmgjVGxOhU1MYZDgqA20ZglGty_bfbIuJ-GNsvPx72pxvkL61OTPM
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/CICC.2008.4672095
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Xplore
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISBN 9781424420193
1424420199
EndPage 358
ExternalDocumentID 4672095
Genre orig-research
GroupedDBID 29O
6IE
6IF
6IH
6IK
6IL
6IM
6IN
AAJGR
AAWTH
ABLEC
ACGFS
ADZIZ
AFFNX
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
IJVOP
IPLJI
M43
OCL
RIE
RIL
RIO
RNS
ID FETCH-LOGICAL-i175t-c7a453cea23d4e71862e180761dcf8bc71b4c04c7662ff94f56961848817d2ef3
IEDL.DBID RIE
ISBN 9781424420186
1424420180
ISSN 0886-5930
IngestDate Wed Aug 27 02:01:34 EDT 2025
IsPeerReviewed false
IsScholarly true
LCCN 85-653738
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i175t-c7a453cea23d4e71862e180761dcf8bc71b4c04c7662ff94f56961848817d2ef3
PageCount 4
ParticipantIDs ieee_primary_4672095
PublicationCentury 2000
PublicationDate 2008-Sept.
PublicationDateYYYYMMDD 2008-09-01
PublicationDate_xml – month: 09
  year: 2008
  text: 2008-Sept.
PublicationDecade 2000
PublicationTitle 2008 IEEE Custom Integrated Circuits Conference
PublicationTitleAbbrev CICC
PublicationYear 2008
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0019982
ssj0000453611
Score 1.9161563
Snippet A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility...
SourceID ieee
SourceType Publisher
StartPage 355
SubjectTerms Circuits
Clocks
CMOS process
Energy consumption
Flip-flops
Large scale integration
Latches
Magnetic separation
Magnetic tunneling
Magnetization
Title Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs
URI https://ieeexplore.ieee.org/document/4672095
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV27TsMwFLVKJ1h4tIi3MjDi1okdO2aNiApSKySo1K2KnWtUUSVRSQf4epwnDzGwJVniXCu-x9fnnIvQdWxcohNfYqFjwIxTghXzKQ4050zSWJHKrHo645M5e1j4ix666bQwAFCRz2BUXlZn-Ummt2WpbGx_as9Cgh20IwJea7W6eoqFJpS7Hb2jlI55NYLk2JeUtKIur3Ssar2emnveHHe6RI7D-zCsKZbN2360XamyTrSPpu14a7LJ62hbqJH--GXl-N8POkDDL32f89hlrkPUg_QI7X2zJhyg21mW2pXLztsanGn8kpZiRydar3IcrbPcsVjXqcoQ6h3nZac1bDYAzlMWvg3RPLp7Die46bOAVxY8FFiL2AZPQ-zRhIFNVtwDGyTB3USbQGnhKqYJ04JzzxjJjM-rPjFB4IrEA0OPUT_NUjhBjtQ0tpDK7jGpYcru5SRJEiWBSgI8EOIUDcooLPPaSmPZBODs78fnaLelZxD3AvWLzRYuLQYo1FU1-Z8GI6dd
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV27TsMwFLVKGYCFR4t4k4ERt07sODFrRNVCUyHRSt2q2LlBFVUSlXSAr8d58hADW5LFyU2ce3x9zrkI3QSRSVRoC-yoADDjlGDJbIpdxTkTNJCkMKv2J3w4Yw9ze95Ct40WBgAK8hn08sNiLz9M1CYvlfX1pLY0JNhC2zZjzC7VWk1FRYMTys2G4JGLx6wSQ3JsC0pqWZeVe1bVbk_VOa82PE0i-t7I80qSZTXej8YrRd4Z7CO_vuOSbvLa22Sypz5-mTn-95EOUPdL4Wc8NbnrELUgPkJ738wJO-huksT636Xf3AoMP3iJc7mjMVgtUzxYJamh0a5RFCLkO07zXms4WgMYz4n31kWzwf3UG-Kq0wJeaviQYeUEOngKAouGDHS64hboIDncDFXkSuWYkinClMO5FUWCRTYvOsW4rumEFkT0GLXjJIYTZAhFAw2q9CqTRkzq1ZwgYSgFUEGAu45zijp5FBZpaaaxqAJw9vfla7QznPrjxXg0eTxHuzVZg5gXqJ2tN3CpEUEmr4oP4RME0qqq
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2008+IEEE+Custom+Integrated+Circuits+Conference&rft.atitle=Nonvolatile+Magnetic+Flip-Flop+for+standby-power-free+SoCs&rft.au=Sakimura%2C+N.&rft.au=Sugibayashi%2C+T.&rft.au=Nebashi%2C+R.&rft.au=Kasai%2C+N.&rft.date=2008-09-01&rft.pub=IEEE&rft.isbn=9781424420186&rft.issn=0886-5930&rft.spage=355&rft.epage=358&rft_id=info:doi/10.1109%2FCICC.2008.4672095&rft.externalDocID=4672095
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0886-5930&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0886-5930&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0886-5930&client=summon