Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

• Published in: IEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
• Main Authors: Sethi, Khushal, Suri, Manan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2019
• Subjects: Classification algorithms; Field programmable gate arrays; Histograms; Memory management; Support vector machines; Training
• ISBN: 9781728103976; 1728103975
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS.2019.8702189

In this paper, we present first-ever optimized hardware implementation of a state-of-the-art neuromorphic approach Histogram of Averaged Time Surfaces (HATS) algorithm to event-based object classification in FPGA for asynchronous time-based image sensors (ATIS). Our Implementation achieves latency of 3.3 ms for the N-CARS dataset samples and is capable of processing 2.94 Mevts/s. Speed-up is achieved by using parallelism in the design and multiple Processing Elements can be added. As development platform, Zynq-7000 SoC from Xilinx is used. The tradeoff between Average Absolute Error and Resource Utilization for fixed precision implementation is analyzed and presented. The proposed FPGA implementation is ∼ 32 × power efficient compared to software implementation.