Highly Reliable Interface of Self-aligned CuSiN process with Low-k Sic barrier dielectric (k3.5) for 65nm node and beyond

A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) has been developed for 65nm node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectr...

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Bibliographic Details
Published inProceedings of the IEEE International Interconnect Technology Conference pp. 125 - 127
Main Authors Usami, T., Ide, T., Kakuhara, Y., Ajima, Y., Ueno, K., Maruyama, T., Yu, Y., Apen, E., Chattopadhyay, K., van Schravendijk, B., Oda, N., Sekine, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Capacitance
Copper
Dielectrics
Optical microscopy
Plasmas
Silicon carbide
Silicon compounds
Surface morphology
Surface resistance
Testing
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ISBN1424401046
9781424401048
ISSN2380-632X
DOI10.1109/IITC.2006.1648665

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Summary:A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) has been developed for 65nm node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure. In addition, 39times via electro-migration (EM) improvement and 1.5times better TZDB were obtained in comparison to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TEM-EELS. According to these analyses, the mechanism for performance enhancement is proposed
ISBN:1424401046
9781424401048
ISSN:2380-632X
DOI:10.1109/IITC.2006.1648665