Reconfigurable Instruction Set Processor Design Using Software Based Configuration

• Published in: 2008 International Conference on Advanced Computer Theory and Engineering pp. 938 - 942
• Main Authors: Iqbal, M.A., Awan, U.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2008
• Subjects: Application software; Coarse-grain; Computer aided instruction; Computer performance; Configurations; Field programmable gate arrays; Fine-grain; FPGA; Hardware; Multi-port Configuration Memory; Process design; RFUs; RISP; Software design; Software performance; Very large scale integration; Yarn
• ISBN: 9780769534893; 0769534899
• ISSN: 2154-7491
• DOI: 10.1109/ICACTE.2008.74

Due to the potential enhancements in the execution of software based applications shown by Reconfigurable Instruction Set Processors (RISPs), reconfigurable computing has become a subject of great deal of research in the field of computer sciences. Its key feature is the ability to perform the computations in hardware to increase the performance on one hand while retaining much of the flexibility of the software on the other hand. The VLSI development is continuously improving and new ways must be obtained to become able to fully take the advantages of the emerging technology. Reconfigurable hardware might be the next step which will give computer performance a big leap forward. The idea is to use the now a daypsilas high performance FPGA technology to adapt the hardware to the problem. This research paper presents an alternative design of a RISP which supports multiple threads running concurrently, all with instant hardware support. Core of Xilinx FPGAs like Virtex series has been used to adapt the possibilities of loading partial hardware configurations while retaining the execution of the remaining active parts of the application.