A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

In this paper, a bus encoding approach including related code generation algorithm for global data busses is developed to produce area-efficient crosstalk-avoidance (CA) codes with considering low-power requirements. Proposed codes are codes with memory using overlapping boundary strategy. The proba...

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Bibliographic Details
Published in2008 International Symposiium on VLSI Design, Automation and Test pp. 172 - 175
Main Authors Kuang-Chin Cheng, Jing-Yang Jou
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2008
Subjects
Capacitance
CMOS technology
Codecs
Crosstalk
Data engineering
Energy consumption
Integrated circuit interconnections
Power generation
Propagation delay
Wires
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ISBN1424416167
9781424416165
DOI10.1109/VDAT.2008.4542440

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Summary:In this paper, a bus encoding approach including related code generation algorithm for global data busses is developed to produce area-efficient crosstalk-avoidance (CA) codes with considering low-power requirements. Proposed codes are codes with memory using overlapping boundary strategy. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2times for heavily coupled busses based on theoretical analysis. As compared to uncoded data words, proposed codes show 12% to 38% energy- reduction on bus for an equi-probable 32-bit bus design.
ISBN:1424416167
9781424416165
DOI:10.1109/VDAT.2008.4542440