Performance Characterization and Optimization of Atomic Operations on AMD GPUs

• Published in: 2011 IEEE International Conference on Cluster Computing pp. 234 - 243
• Main Authors: Elteir, M., Heshan Lin, Wu-Chun Feng
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2011
• Subjects: Arrays; atomic operations; GPGPU; GPU; Graphics processing unit; heterogeneous computing; High definition video; Instruction sets; Kernel; MapReduce; Synchronization
• ISBN: 9781457713552; 1457713551
• ISSN: 1552-5244
• DOI: 10.1109/CLUSTER.2011.34

Atomic operations are important building blocks in supporting general-purpose computing on graphics processing units (GPUs). For instance, they can be used to coordinate execution between concurrent threads, and in turn, assist in constructing complex data structures such as hash tables or implementing GPU-wide barrier synchronization. While the performance of atomic operations has improved substantially on the latest NVIDIA Fermi-based GPUs, system-provided atomic operations still incur significant performance penalties on AMD GPUs. A memory-bound kernel on an AMD GPU, for example, can suffer severe performance degradation when including an atomic operation, even if the atomic operation is never executed. In this paper, we first quantify the performance impact of atomic instructions to application kernels on AMD GPUs. We then propose a novel software-based implementation of atomic operations that can significantly improve the overall kernel performance. We evaluate its performance against the system-provided atomic using two micro-benchmarks and four real applications. The results show that using our software based atomic operations on an AMD GPU can speedup an application kernel by 67-fold over the same application kernel but with the (default) system-provided atomic operations.