Incorporating Instruction-Based Sampling into AMD CodeAnalyst

Instruction-Based Sampling (IBS) is a hardware mechanism that improves the accuracy of profiles. IBS is supported by AMD Family 10h processors. The processing pipeline of an AMD Family 10h processor is separated into two loosely coupled phases: A front-end phase that fetches AMD64 instruction bytes...

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Bibliographic Details
Published in2010 IEEE International Symposium on Performance Analysis of Systems and Software pp. 119 - 120
Main Authors Drongowski, Paul, Lei Yu, Swehosky, Frank, Suthikulpanit, Suravee, Richter, Robert
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2010
Subjects
Application software
Counting circuits
Delay
Hardware
Microarchitecture
Performance analysis
Personal communication networks
Pipelines
Sampling methods
Software performance
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ISBN1424460239
9781424460236
DOI10.1109/ISPASS.2010.5452049

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Summary:Instruction-Based Sampling (IBS) is a hardware mechanism that improves the accuracy of profiles. IBS is supported by AMD Family 10h processors. The processing pipeline of an AMD Family 10h processor is separated into two loosely coupled phases: A front-end phase that fetches AMD64 instruction bytes and a back-end phase that execute "ops" which issue from decoded AMD64 instructions. An op is an internal, fixed-width instruction which is executed by the pipeline stages in the execution phase. More than one op may issue from an instruction. Due to the decoupling, IBS samples fetches and ops separately, i.e., there are two independent sampling mechanisms. We will concentrate on IBS op sampling in this discussion.
ISBN:1424460239
9781424460236
DOI:10.1109/ISPASS.2010.5452049