Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

• Published in: 2009 IEEE International Conference on IC Design and Technology pp. 165 - 168
• Main Authors: Song, S.C., Abu-Rahma, M., Han, B.M., Ge, L., Yoon, S.S., Wang, J., Yang, W., Liu, D., Hu, C., Yeap, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: 22nm; 32nm; Bitcell; Degradation; Design methodology; Electrostatics; FinFET; FinFETs; Icell; Leakage current; Manufacturing; MuGFET; Optimization methods; Random access memory; SNM; SRAM; Stability; Threshold voltage; Vccmin
• ISBN: 1424429331; 9781424429332
• ISSN: 2381-3555
• DOI: 10.1109/ICICDT.2009.5166287

Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell < 0.1 mum 2 below 32 nm node.