Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS

This paper addresses the problem of minimizing the total energy consumption of a (chip) multiprocessor system while maintaining a required throughput. The minimum energy solution subject to a throughput constraint is achieved by selectively turning cores ON or OFF, assigning a given set of tasks to...

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Bibliographic Details
Published in2010 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 49 - 52
Main Authors Ghasemazar, M, Pakbaznia, E, Pedram, M
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2010
Subjects
Clocks
Energy consumption
Energy management
Frequency
Multiprocessing systems
NP-hard problem
Power system management
Throughput
Turning
Voltage
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ISBN1424453089
9781424453085
ISSN0271-4302
DOI10.1109/ISCAS.2010.5537096

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Summary:This paper addresses the problem of minimizing the total energy consumption of a (chip) multiprocessor system while maintaining a required throughput. The minimum energy solution subject to a throughput constraint is achieved by selectively turning cores ON or OFF, assigning a given set of tasks to different cores, and simultaneously selecting the optimum operating supply voltage and clock frequency level for each processor core in the system. This NP-hard problem is solved by a three-level hierarchical framework comprised of a control theory-based dynamic power manager (DPM) and a task assignment unit. Experimental results demonstrate 17% energy saving of the proposed solution approach.
ISBN:1424453089
9781424453085
ISSN:0271-4302
DOI:10.1109/ISCAS.2010.5537096