APA (7th ed.) Citation

Gill, S. S., Chandel, R., Chandel, A., & Sandhu, P. S. (2010). Simulated annealing based delay centric VLSI circuit partitioning. 2010 3rd IEEE International Conference on Computer Science and Information Technology, 1, 1-4. https://doi.org/10.1109/ICCSIT.2010.5563874

Chicago Style (17th ed.) Citation

Gill, S S., R. Chandel, A. Chandel, and P S. Sandhu. "Simulated Annealing Based Delay Centric VLSI Circuit Partitioning." 2010 3rd IEEE International Conference on Computer Science and Information Technology 1 (2010): 1-4. https://doi.org/10.1109/ICCSIT.2010.5563874.

MLA (9th ed.) Citation

Gill, S S., et al. "Simulated Annealing Based Delay Centric VLSI Circuit Partitioning." 2010 3rd IEEE International Conference on Computer Science and Information Technology, vol. 1, 2010, pp. 1-4, https://doi.org/10.1109/ICCSIT.2010.5563874.