Simulated annealing based delay centric VLSI circuit partitioning

Two way partitioning of a circuit represented as a graph, has been carried out using simulated annealing in the present work. The problem is solved in such a way that delay between the partitions is minimum. The parameters used in the annealing process are initial temperature, cooling rate, and thre...

Full description

Saved in:
Bibliographic Details
Published in2010 3rd IEEE International Conference on Computer Science and Information Technology Vol. 1; pp. 1 - 4
Main Authors Gill, S S, Chandel, R, Chandel, A, Sandhu, P S
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2010
Subjects
Cooling
Delay
netlist
partitioning
Simulated annealing
VLSI
Online AccessGet full text
ISBN9781424455379
1424455375
DOI10.1109/ICCSIT.2010.5563874

Cover

More Information
Summary:Two way partitioning of a circuit represented as a graph, has been carried out using simulated annealing in the present work. The problem is solved in such a way that delay between the partitions is minimum. The parameters used in the annealing process are initial temperature, cooling rate, and threshold. The influence of these parameters on the delay between the partitions is evaluated. The method is tested on a test case with 102 components connected by 103 nets. Substantial improvement in delay has been obtained over the initial circuit delay justifying the effectiveness of proposed method.
ISBN:9781424455379
1424455375
DOI:10.1109/ICCSIT.2010.5563874