Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture

• Published in: 2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings pp. 10 - 15
• Main Authors: Ramagundam, Shashisekhar, Das, Sunil R., Morton, Scott, Biswas, Satyendra N., Groza, Voicu, Assaf, Mansour H., Petriu, Emil M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2014
• Subjects: Advanced microcontroller bus architecture (AMBA) high-performance bus (AHB); Educational institutions; field programmable gate array (FPGA); finite-state machines (FSMs); memory controller (MC); Memory management; Microcontrollers; Random access memory; Read only memory; System-on-chip; system-on-chips (SOCs)
• ISSN: 1091-5281
• DOI: 10.1109/I2MTC.2014.6860513

The on-chip interconnection system known as advanced microcontroller bus architecture (AMBA) is a well-established open specification for the proper management of functional blocks comprising system-on-chips (SOCs). In the subject paper, the design and implementation details of AMBA high-performance bus (AHB) master and slave with memory controller (MC) interface are discussed. A bridge between AHB master and slave with supportive application of MC is also proposed and the resultant efficiency in respect of area overhead and speed is provided. The realization of the control structure is based on the concept of conventional finite state machines (FSMs). The intellectual property (IP) blocks of AHB master and slave are implemented on a Xilinx Spartan3 field programmable gate array (FPGA) chip (3s50pq208-5).