Optimized reversible vedic multipliers for high speed low power operations

• Published in: 2013 IEEE Conference on Information and Communication Technologies pp. 809 - 814
• Main Authors: Saligram, Rakshith, Rakshith, T. R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2013
• Subjects: Adders; Communications technology; Conferences; Digital signal processing; Logic circuits; Logic gates; Optimized Design; Quantum Computing; Reversible Logic Gate; Signal processing algorithms; TRLIC; Urdhva Tiryakbhayam
• ISBN: 9781467357593; 1467357596
• DOI: 10.1109/CICT.2013.6558205

Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.