Timing yield enhancement through soft edge flip-flop based design

The first evaluation of a soft-edge flip-flop is presented as an alternative to useful-skew and latch-based designs for variation compensation in a 16-bit 8-tap FIR filter in 0.13 mum CMOS. An 11.2% performance improvement was achieved over a standard hard edge data flip-flop (9.2% when post-silicon...

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Bibliographic Details
Published in2008 IEEE Custom Integrated Circuits Conference pp. 543 - 546
Main Authors Wieckowski, M., Young Min Park, Tokunaga, C., Dong Woon Kim, Zhiyoong Foo, Sylvester, D., Blaauw, D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
Circuits
Clocks
Delay effects
Flip-flops
Latches
Master-slave
Performance analysis
Pipelines
Pulse generation
Timing
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ISBN9781424420186
1424420180
ISSN0886-5930
DOI10.1109/CICC.2008.4672142

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Summary:The first evaluation of a soft-edge flip-flop is presented as an alternative to useful-skew and latch-based designs for variation compensation in a 16-bit 8-tap FIR filter in 0.13 mum CMOS. An 11.2% performance improvement was achieved over a standard hard edge data flip-flop (9.2% when post-silicon useful-skew is applied).
ISBN:9781424420186
1424420180
ISSN:0886-5930
DOI:10.1109/CICC.2008.4672142