Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring

• Published in: 2007 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1049 - 1052
• Main Authors: Tang, Wai-Chung, Lo, Wing-Hang, Wu, Yu-Liang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2007
• Subjects: Circuit synthesis; Circuit testing; Computer science; Delay; Field programmable gate arrays; Logic circuits; Logic testing; Minimization methods; Table lookup; Wire
• ISBN: 1424409209; 9781424409204
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2007.378150

FPGA technology mapping is conventionally solved without altering the circuit by modeling the circuit as a direct acyclic graph for the ease of applying graph algorithms. Clearly there is room for further improvement on even optimal technology mapping results if logic perturbation can be applied. In this paper, we propose logic-aware minimization methods to further reduce both depth and area for the purely-graph-based depth-optimal FPGA mapped results. For area minimization, the proposed method perturbs the subject circuit using rewiring technique and incrementally reduce the mapping area. Improving the outstanding technology mapping algorithm DAOMap, the method can further reduce area by 10.9%. An area reduction of 13.4% is achieved with synthesis results from BDS-pga. A logic level reduction scheme is also proposed and it further reduces LUT depth for half of the circuits tested without area penalty. A combination of logic level reduction and area minimization techniques can improve both the LUT depth and area by 11.3% and 6.1%, compared to results of FlowMap and FlowSYN respectively.