Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B 2 H 6 -based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide re...

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Bibliographic Details
Published inESSDERC 2007 - 37th European Solid State Device Research Conference pp. 259 - 262
Main Authors Yong Soo Kim, Kwan-Yong Lim, Min-Gyu Sung, Soo-Hyun Kim, Hong-Seon Yang, Heung-Jae Cho, Se-Aug Jang, Jae-Geun Oh, Kwangok Kim, Young-Kyun Jung, Tae-Woo Jung, Choon-Hwan Kim, Doek-Won Lee, Won Kim, Young-Hoon Kim, Kang-Sik Choi, Tae-Kyung Oh, Yun-Taek Hwang, Seung-Ho Pyi, Ja-chun Ku, Jin-Woong Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2007
Subjects
Annealing
Capacitance measurement
Chemical vapor deposition
Current measurement
Delay
Electric resistance
Electrical resistance measurement
Hydrogen
Random access memory
Tungsten
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ISBN1424411238
9781424411238
ISSN1930-8876
DOI10.1109/ESSDERC.2007.4430927

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Summary:We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B 2 H 6 -based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.
ISBN:1424411238
9781424411238
ISSN:1930-8876
DOI:10.1109/ESSDERC.2007.4430927