Low-Latency FPGA Based Financial Data Feed Handler

• Published in: 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines pp. 93 - 96
• Main Authors: Pottathuparambil, R, Coyne, J, Allred, J, Lynch, W, Natoli, V
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Algorithm design and analysis; Bridges; Feeds; Field programmable gate arrays; FPGA; Generators; Hardware; ITCH feed handler; Low-latency Trading; Monitoring
• ISBN: 9781612842776; 1612842771
• DOI: 10.1109/FCCM.2011.50

Financial exchanges provide real time data feeds containing trade, order and status information to brokers, traders and other market makers. ITCH is one such market data feed that is disseminated by the NASDAQ exchange. The work presented in this paper describes an FPGA based ITCH feed handler and processing system. The handler, built on the Stone Ridge RDX-11 hardware platform with a combination of HDL and Impulse C, accepts and processes ITCH packet sat line speed with extremely low latency. Our implementation parses sixteen different stock symbols in the feed and generates an outbound packet on the NASDAQ one second heartbeat. The unit was tested with an artificial feed that could be adjusted in speed to simulate market surges. The system demonstrated a turnaround latency of 2.7μs with very little variation for all tested feed rates. The CPU equivalent demonstrated 38±22μs(1x rate) with a long tail illustrating the variability inherent to processing by the host O/S. The FPGA solution demonstrated ultra-low, deterministic latency and was able to continue processing data at the line rate limit.