A flexible decoder IC for WiMAX QC-LDPC codes

• Published in: 2008 IEEE Custom Integrated Circuits Conference pp. 527 - 530
• Main Authors: Tzu-Chieh Kuo, Willson, A.N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2008
• Subjects: Clocks; CMOS technology; Code standards; Computer architecture; Energy efficiency; Iterative algorithms; Iterative decoding; Parity check codes; Power dissipation; WiMAX
• ISBN: 9781424420186; 1424420180
• ISSN: 0886-5930
• DOI: 10.1109/CICC.2008.4672138

A programmable and power-efficient decoder IC employing the layered-decoding message-passing algorithm and the low-complexity offset-based Min-Sum check algorithm for irregular QC-LDPC codes is presented. The iterative decoder can be reconfigured to decode all the QC-LDPC codes defined in the Mobile WiMAX standard. Specifically, the decoder achieves a throughput of 68 Mbps at a 100-MHz clock rate for the rate-1/2 length-2304 code with ten iterations, and occupies a core area of 3.4 mm 2 in 0.18-mum CMOS technology and dissipates estimated 165 mW from a 1.8-V supply. It is 53% smaller, 86% lower in complexity, and has better energy efficiency than other published WiMAX LDPC decoder ASICs, to the best of our knowledge.