High radix booth multipliers using reduced area adder trees

• Published in: Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers Vol. 1; pp. 545 - 549 vol.1
• Main Authors: Gallagher, W.L., Swartzlander, E.E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1994
• Subjects: Algorithm design and analysis; Costs; Counting circuits; Hardware; Logic
• ISBN: 0818664053; 9780818664052
• ISSN: 1058-6393
• DOI: 10.1109/ACSSC.1994.471512

The reduced area multiplier, the Wallace multiplier, and the Dadda (1965) multiplier each offer fast multiplication of signed binary numbers with the use of a large adder tree and a carry lookahead adder. However, their complexity makes them undesirable for some applications. A Booth (1951) multiplier, on the other hand, offers simplicity and flexibility, by both breaking a multiplication up into pieces, and by allowing the size of the pieces to be chosen. Unfortunately, Booth multipliers become difficult to design for higher radices. The use of a fast adder tree, such as that found in a reduced area multiplier, permits straightforward design of very high radix Booth multipliers. Increasing the radix of a Booth multiplier in this manner results in large increases in speed with reasonable hardware cost.< >