Automated formal synthesis of Wallace Tree multipliers

In this paper, we present a formal synthesis methodology that is capable of performing correct synthesis at almost all levels of abstraction and can be adapted to be used for most of the combinational digital circuits irrespective of their size and complexity. The proposed methodology calls for prov...

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Bibliographic Details
Published in2007 50th Midwest Symposium on Circuits and Systems pp. 293 - 296
Main Authors Hasan, O., Kort, S.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.08.2007
Subjects
Bridge circuits
Character generation
Circuit synthesis
Digital circuits
Embedded software
Hardware design languages
Software algorithms
Software performance
Software tools
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ISBN1424411750
9781424411757
ISSN1548-3746
DOI10.1109/MWSCAS.2007.4488591

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Summary:In this paper, we present a formal synthesis methodology that is capable of performing correct synthesis at almost all levels of abstraction and can be adapted to be used for most of the combinational digital circuits irrespective of their size and complexity. The proposed methodology calls for proving the correctness-preserving characteristic for the transformations that are required in the synthesis of a particular digital circuit in a higher-order-logic theorem prover. These correctness- preserving transformation proofs can then be used to automatically verify the correctness of the corresponding synthesis process within the theorem prover in an automated way. For illustration purposes, we present the construction of an automated formal synthesis tool for Wallace Tree multipliers based on our methodology.
ISBN:1424411750
9781424411757
ISSN:1548-3746
DOI:10.1109/MWSCAS.2007.4488591