A novel clock deskew method by linear programming

• Published in: 2007 50th Midwest Symposium on Circuits and Systems pp. 1261 - 1264
• Main Authors: Hashizume, Y., Takashima, Y., Nakamura, Y.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.08.2007
• Subjects: Circuit optimization; Clocks; Costs; Delay lines; Deskew; Fabrication; Fuses; Linear programming; Linear Programming (LP); Programmable Delay Element (PDE); Switches; Testing; Timing
• ISBN: 1424411750; 9781424411757
• ISSN: 1548-3746
• DOI: 10.1109/MWSCAS.2007.4488782

Since the process technology of LSI devices are developing, the process variation becomes a more critical issue. Especially, the clock skew, which is produced by fabrication variation, causes the serious defects for fabricated chip functions. To improve this problem, the several deskew methods using programmable delay elements (PDEs) have been proposed. However, they need much test cost and PDE cost for an industrial application. We propose a novel method with less PDEs and less test cost by linear programming (LP). The proposed method calculates the each PDE delay using the feasibility check of LP. Our experiment shows that the nondefective chip rate after applying deskew increase 91.6% with 4 PDEs while the nondefective chip rate before applying deskew are 21.2%. The experimental result confirms that our proposed method is effective for improving the yields and relaxing the design margin.