A multi-path fused add-subtract unit for Digital Signal Processing

The task of computing both the summation and difference of a pair of Floating-Point (FP) data is often needed in some Digital Signal Processing (DSP) algorithms and other applications. A basic fused add-subtract unit (FAS) is introduced [1] to perform simultaneously both addition and subtraction ope...

Full description

Saved in:
Bibliographic Details
Published in2012 IEEE International Conference on Computer Science and Automation Engineering Vol. 3; pp. 448 - 452
Main Authors Yao Tao, Gao Deyuan, Fan Xiaoya
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.05.2012
Subjects
Adders
Computer architecture
Delay
Digital signal processing
Equations
FAS unit
Floating-Point
Hardware
Signal processing algorithms
Online AccessGet full text
ISBN1467300888
9781467300889
DOI10.1109/CSAE.2012.6272991

Cover

More Information
Summary:The task of computing both the summation and difference of a pair of Floating-Point (FP) data is often needed in some Digital Signal Processing (DSP) algorithms and other applications. A basic fused add-subtract unit (FAS) is introduced [1] to perform simultaneously both addition and subtraction operation for a couple of operands and has less hardware overhead than the general approach using two FP adders. In this paper, a novel multi-path FAS unit is presented to accelerate the basic FAS architecture. The implementation results in FP single precision data format show that the multi-path FAS is 48.7% faster and 16.9% smaller than the basic FAS unit.
ISBN:1467300888
9781467300889
DOI:10.1109/CSAE.2012.6272991