Addressing thermal and power delivery bottlenecks in 3D circuits

The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat...

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Bibliographic Details
Published in2009 Asia and South Pacific Design Automation Conference pp. 423 - 428
Main Author Sapatnekar, S.S.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.01.2009
Subjects
Equations
Finite difference methods
Packaging
Power generation
Power grids
Steady-state
Temperature
Thermal conductivity
Thermal management
Three-dimensional integrated circuits
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ISBN9781424427482
1424427487
ISSN2153-6961
DOI10.1109/ASPDAC.2009.4796518

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Summary:The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits.
ISBN:9781424427482
1424427487
ISSN:2153-6961
DOI:10.1109/ASPDAC.2009.4796518