Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures

• Published in: 2011 International Conference on Reconfigurable Computing and FPGAs pp. 135 - 140
• Main Authors: Schweizer, Thomas, Schlicker, Philipp, Eisenhardt, Sven, Kuhn, Tommy, Rosenstiel, Wolfgang
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.11.2011
• Subjects: coarse-grained; Computer architecture; Context; error detection; Fault tolerant systems; fault-tolerance; Power demand; reconfigurable; Redundancy; reliability; TMR; Tunneling magnetoresistance
• ISBN: 9781457717345; 1457717344
• ISSN: 2325-6532
• DOI: 10.1109/ReConFig.2011.57

Hardware redundancy is a common method for improving the reliability of a system. The disadvantage of this approach is the hardware overhead and the additional power consumption. This contribution proposes a strategy for implementing low-cost triple modular redundancy (TMR) on coarse-grained reconfigurable architectures (CGRAs). Low-cost TMR is achieved by utilizing unused functional units (FUs) for the redundant computation of results. This is realized by combining the FUs of three processing elements in a fault-tolerant data path. Experimental results show that the proposed approach reduces area in a 8-bit architecture by 12.8% and average power consumption is decreased between 1.6 and 18.6% when compared with a fault-tolerant CGRA implemented by conventional TMR.