Design and implementation of efficient multiplier using Vedic mathematics

• Published in: 3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011) pp. 162 - 166
• Main Authors: Rudagi, J.M, Ambli, V, Munavalli, V, Patil, R, Sajjan, V
• Format: Conference Proceeding
• Language: English
• Published: Stevenage IET 2011; The Institution of Engineering & Technology
• Subjects: Digital arithmetic methods; Digital signal processing; Logic and switching circuits; Logic circuits; Signal processing and detection; real-time signal applications; multiplying circuits; DSP chip; signal processing; Multiply and Accumulate; fast multiplier circuit; key arithmetic operations; high speed multiplier; digital arithmetic; FFT; computation intensive arithmetic functions; microprocessors; vedic mathematics; filtering; digital signal processing; logic unit; signal processing applications; DSP algorithms; high speed processing; multiplier design; multiplication-based operations; DSP applications; MAC; fast Fourier transform; multiplication time; fundamental function; image processing applications; computer applications; multiplier implementation; instruction cycle time
• ISBN: 8191069180; 9788191069181
• DOI: 10.1049/ic.2011.0071

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).