Current trends in high-level synthesis of asynchronous circuits

• Published in: 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) pp. 347 - 350
• Main Author: Sparso, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2009
• Subjects: Asynchronous circuits; Buildings; Circuit synthesis; Clocks; High level synthesis; Integrated circuit interconnections; Large-scale systems; Registers; Tides; Voltage
• ISBN: 9781424450909; 142445090X
• DOI: 10.1109/ICECS.2009.5411011

This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e.g. the Haste/TiDE tool from Handshake Solutions or the Balsa tool from the University of Manchester. The aims are to add high-level synthesis capabilities to these tools and to extend the tools such that a wider range of (higher speed) micro-architectures can be generated. Another branch of research takes a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly continuous-time asynchronous circuits that operate without a clock. The perspective here is that the substitution/conversion is done as the final step in an otherwise conventional synchronous design flow.