ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits

• Published in: Proceedings - International Test Conference pp. 268 - 277
• Main Authors: Lei, Jun-Yang, Chatterjee, Abhijit
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2022
• Subjects: analog bug diagnosis; Analog/RF design validation; Clustering algorithms; Computer bugs; Emulation; Inspection; machine learning; Performance evaluation; Silicon; Technological innovation; test generation
• ISSN: 2378-2250
• DOI: 10.1109/ITC50671.2022.00035

In analog and mixed-signal (AMS) design, it is necessary to validate equivalence between the behavioral or netlist level description of an AMS system and its physical realization (device-under test, DUT) in silicon. If a discrepancy is found, relevant bugs need to be diagnosed to individual circuit modules for closer inspection. Typically, design bugs may exist in one or more circuit modules. In addition, parametric defects in silicon can also cause performance degradation. So a combination of such design "anomalies" needs to be debugged and triaged during silicon respin. A major difficulty is that neither the number of buggy modules, nor the nature of buggy module behaviors is known apriori. To diagnose and localize such bugs, we perform a set of bug emulation experiments (BEEs). In each experiment, one or more learning kernels are placed across modules in the high-level AMS model of the circuit and trained to replicate the buggy circuit output response to specialized test stimulus (this is a key innovation: concurrent bug learning). The test stimulus is optimized to expose behavioral differences between the expected and observed DUT response over the entire input space of the DUT. An error response clustering algorithm along with knowledge of the placement of the kernels is then used to guide successive BEEs for bug diagnosis. The algorithm converges when the minimum residual error across the ensemble of BEEs conducted cannot be further reduced through additional BEEs. The modules with inserted kernels for that BEE are the most likely buggy modules. Results on multiple mixed-signal designs prove the viability of the proposed approach.