Flash fast-locking digital PLL using LT SPICE

A flash fast-locking digital phase-locked loop (DPLL) is presented using transistor level 50 nm CMOS technology and 1V power supply in LT SPICE. The DPLL operation includes two stages: (1) a coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in fla...

Full description

Saved in:
Bibliographic Details
Published in2015 11th International Computer Engineering Conference (ICENCO) pp. 229 - 234
Main Authors Wagdy, Mahmoud Fawzy, Kabeer, Syed Zeeshan Ahmed
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2015
Subjects
CMOS
CMOS integrated circuits
CMOS technology
coarse tuning
Computational modeling
DPLL
fast-locking
fine tuning
flash algorithm
frequency tracking
lock time
LT SPICE
Manuals
phase tracking
PLL
SPICE
transistor level
Voltage control
Voltage-controlled oscillators
Online AccessGet full text
DOI10.1109/ICENCO.2015.7416353

Cover

More Information
Summary:A flash fast-locking digital phase-locked loop (DPLL) is presented using transistor level 50 nm CMOS technology and 1V power supply in LT SPICE. The DPLL operation includes two stages: (1) a coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage consists of frequency comparator array, a priority encoder, a digital-to-analog converter (DAC), and control logic (CL). Design considerations and implementations are presented in this paper. The fast-locking flash DPLL reduces the lock time by a factor of about 2.19 when compared with the conventional DPLL counterpart, in the frequency range 80 MHz-1.1 GHz.
DOI:10.1109/ICENCO.2015.7416353