A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical pa...

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Bibliographic Details
Published in2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) pp. 1 - 4
Main Authors Fujiwara, Koichi, Kawamura, Kazushi, Yanagisawa, Masao, Togawa, Nozomu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Algorithm design and analysis
Clocks
Delays
Field programmable gate arrays
Integrated circuit interconnections
Registers
Wires
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DOI10.1109/VLSI-DAT.2016.7482547

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Summary:High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.
DOI:10.1109/VLSI-DAT.2016.7482547