Gate-level modelling of NBTI-induced delays under process variations

• Published in: 2016 17th Latin-American Test Symposium (LATS) pp. 75 - 80
• Main Authors: Copetti, Thiago, Medeiros, Guilherme, Bolzani Poehls, Leticia, Vargas, Fabian, Kostin, Sergei, Jenihhin, Maksim, Raik, Jaan, Ubar, Raimund
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2016
• Subjects: aging; Computational modeling; Degradation; Delays; Integrated circuit modeling; Logic gates; MOSFET; NBTI; reliability; SPICE; static timing analysis
• DOI: 10.1109/LATW.2016.7483343

Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). Moreover, the impact of NBTI is exacerbated by Process Variation (PV), i.e. variations on transistor attributes during the manufacturing process. In this paper, a hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed. The model is applied in order to identify NBTI-critical logic paths of ICs that are subject to aging mitigation techniques. The model is derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. The experimental results demonstrate an accurate fitting between the analysis performed on the proposed gate-level model and the electrical simulations, while the gate-level analysis provides for several orders of magnitude speed-up in simulation.