FPGA implementation of blob detection algorithm for object detection in visual navigation

• Published in: 2013 International conference on Circuits, Controls and Communications (CCUBE) pp. 1 - 5
• Main Authors: Kiran, Divya, Rasheed, Abdul Imran, Ramasangu, Hariharan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2013
• Subjects: Blob detection; Field programmable gate arrays; Labeling; Logic gates; Navigation; Object detection; Pipeline processing; Random access memory; System-on-chip; Visual navigation
• DOI: 10.1109/CCUBE.2013.6718570

Visual navigation system is widely used in various applications such as traffic surveillance, guidance of autonomous vehicles etc. Object detection is one of the important steps which identifies obstacle and provides information about obstacle's location in the image scenario. Blob detection method has been chosen to detect object and to extract required information about the object. Implementation of blob detection algorithm on FPGA requires more hardware resources in terms of number for logic gates etc. In this paper, a modification has been proposed for effective hardware implementation of centroid and area computations while using blob detection algorithm. The proposed approach utilizes a novel way to label the connected components and leads to effective hardware implementation. The proposed algorithm utilizes fewer resources and takes less computational time. This algorithm has been implemented in Xilinx Virtex V FPGA board which operates at 100MHz. Processing time taken by the algorithm for computing area and centroid of objects along with labeling is 0.22ms for image resolution of 100 × 100. Algorithm utilizes 4% of available hardware resource and 4 block RAM for complete processing.