Trubol: Synthesis of Pipelined Circuits from Python-based DSL Specifications

Hardware accelerators can achieve higher energy efficiency on individual tasks compared to general-purpose processors. In this respect, approaches for the fast design of such accelerators are of interest. Hardware description languages are too low-level and do not provide fast design space explorati...

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Bibliographic Details
Published in2023 5th International Conference on Control Systems, Mathematical Modeling, Automation and Energy Efficiency (SUMMA) pp. 490 - 494
Main Author Sovietov, Peter N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 08.11.2023
Subjects
DSL
DSL compiler
Energy efficiency
FPGA
hardware accelerator
hardware DSL
High level synthesis
HLS
Linear programming
Mathematical models
pipeline synthesis
Program processors
Space exploration
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DOI10.1109/SUMMA60232.2023.10349644

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Summary:Hardware accelerators can achieve higher energy efficiency on individual tasks compared to general-purpose processors. In this respect, approaches for the fast design of such accelerators are of interest. Hardware description languages are too low-level and do not provide fast design space exploration. High level synthesis tools are overly universal and often focused on supporting particular chip types. This paper proposes the use of Trubol, a domain-specific language and a compiler for generating Verilog code based on function pipelining. In Trubol it's possible to support different chip types and choose from various pipeline control flow schemes. The practical use of Trubol is illustrated with example implementations of the CORDIC and SHA256 algorithms. For these implementations, a design space exploration was performed. Compared to Vitis HLS, Trubol compiler allows reducing the depth of the synthesized pipeline up to 1.5 times on the SHA256 implementation.
DOI:10.1109/SUMMA60232.2023.10349644