Development of an Iteration Based Design Algorithm for High Frequency Transformer Incorporated in Solid State Transformer

• Published in: 2024 1st International Conference on Trends in Engineering Systems and Technologies (ICTEST) pp. 01 - 07
• Main Authors: Joseph, Sherin, John, Shajimon K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11.04.2024
• Subjects: brute force algorithm; Costs; Force; high freuuency transformer; Mathematical models; Power electronics; Smart-grid; Software; Software algorithms; solid state transformer; total owning cost; Transformer cores
• DOI: 10.1109/ICTEST60614.2024.10576082

Solid State Transformer(SST) is a key element in evolving smart-grid system due to its control and communication capability along with the conventional power transfer operation. The control of power flow is achieved by the incorporation power electronic converters at either sides of the transformer. The transformers used in SST is of high frequency type to reduce the size, weight and volume. This transformer which is incorporated in SST is known as High Frequency Transformer (HFT). For the optimum design of SST, of a specific power and voltage rating, the power electronic switches used are of specific ratings, so the optimum design of HFT determines the optimum design of SST. This paper details the optimum design of a high frequency transformer for the design of solid state transformer. The objective function considered for the optimization of HFT is minimization of Total Owning Cost (TOC). The optimum design is generated from an iterative algorithm, which is developed using Brute Force Technique. A case study is performed in a 1000kVA, 11kV/415V SST by varying different parameters such as magnetic materials, AC test voltage, load factor etc. The validation of the optimum design developed is done in Ansys Maxwell software and the results are comparable with the optimum design developed from the iterative algorithm.