Implementation of Efficient Restoring and Long Division Algorithm

• Published in: International Conference on Computing, Communication, and Networking Technologies (Online) pp. 1 - 6
• Main Authors: Neelima, N., Kumar, Aruru Sai, Jayanth, A., Mahitha, K. Krishna, Reddy, A. Dilip Kumar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.07.2023
• Subjects: Area(LUT); Arithmetic; Circuit optimization; Delay; Delay effects; Hardware design languages; Length measurement; Long division algorithm; Registers; Restoring division; Time measurement; Verilog HDL
• ISSN: 2473-7674
• DOI: 10.1109/ICCCNT56998.2023.10308155

The basic elements of an electronic system are arithmetic operations. Arithmetic operations are the building block of any electronic application and algorithm is a sequence of instructions used to carry out calculations or solve problems. Division implementation has received less attention than the other arithmetic operations, despite the fact that addition, subtraction, multiplication, and division are essential components of arithmetic implementation in the electronic system. If we divide two integers using the procedure, a quotient as well as a remainder is produced. Implementing division operations is quite difficult; in this case, a sophisticated technique is used for implementation success. A successful system must have good division circuit performance. In this research work, the Restoring division and long division algorithm Class are implemented for nsigned integers with data sizes of 8-bit, 16-bit, 32 bit and 64-bit using Verilog HDL language. Three registers named A, Q and M are used for the computation in both the algorithms.