A Design of Power-Efficient AES Algorithm on Artix-7 FPGA for Green Communication

With the development and growth in industries, the society and the environment are facing two huge problems. Advancement in technology have raised the problem of communication and data over safe channels. The power/energy deficiency can be reduced by the practice of Green Communication (GC) technolo...

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Bibliographic Details
Published in2021 International Conference on Technological Advancements and Innovations (ICTAI) pp. 561 - 564
Main Authors Kumar, Keshav, Kaur, Amanpreet, Ramkumar, K. R., Shrivastava, Anurag, Moyal, Vishal, Kumar, Yogendra
Format Conference Proceeding
LanguageEnglish
Published IEEE 10.11.2021
Subjects
AES algorithm
Clock speed
Encryption
Energy efficiency
FPGA
Green products
Hardware
Logic gates
Performance evaluation
Power
Technological innovation
VIVADO
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DOI10.1109/ICTAI53825.2021.9673435

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Summary:With the development and growth in industries, the society and the environment are facing two huge problems. Advancement in technology have raised the problem of communication and data over safe channels. The power/energy deficiency can be reduced by the practice of Green Communication (GC) technologies and energy efficient comopnents. This paper focuses on the use of these technologies in one framework. In this article a power-efficient Advanced Encryption Standard (AES) algorithm is realized on hardware device. For hardware implementations, Field Programmable Gate Array (FPGA) devices are considered. The AES algorithm is designed on VIVADO tool and the results are analyzed on 28 nanometer (nm) Artix-7 FPGA. The power calculation of the AES algorithm is calculated for different clock speed of the device. And it is detected that the AES algorithm is energy efficient, when the clock speed is 2.0ns for Artix-7 FPGA.
DOI:10.1109/ICTAI53825.2021.9673435