Optimization of Advanced Encryption Standard Algorithm (AES) on Field Programmable Gate Array (FPGA)

In this paper, we have proposed high speed Advanced Encryption Standard (AES) hardware architecture by using parallelism in the process. National Institute of Standards and Technology (NIST) cases are predefined inside the module will be selected by test case bits, according to test case bit selecti...

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Bibliographic Details
Published in2019 International Conference on Communication and Electronics Systems (ICCES) pp. 1086 - 1090
Main Authors Jain, Neelesh, Ajnar, D. S., Jain, P. K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2019
Subjects
AES
ARTIX-7
FPGA
NIST
VHDL
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DOI10.1109/ICCES45898.2019.9002397

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Summary:In this paper, we have proposed high speed Advanced Encryption Standard (AES) hardware architecture by using parallelism in the process. National Institute of Standards and Technology (NIST) cases are predefined inside the module will be selected by test case bits, according to test case bit selection, the key and input will be selected, and module generate corresponding output and clock cycles reduces to 44 cycles. AES Algorithm synthesized using VHDL Code and targeted into FPGA. For Synthesis and Simulation Xilinx Design Suit Version 14.7 is used. The design has been Successfully tested on ARTIX-7 FPGA.
DOI:10.1109/ICCES45898.2019.9002397