EFSM Model Construction Method for RTL Digital Circuit

• Published in: International Conference on Dependable Systems and Their Applications (Online) pp. 94 - 105
• Main Authors: Li, Xiaochen, Zhao, Ruilian, Shang, Ying
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2022
• Subjects: Analytical models; Behavioral sciences; digital circuit; extended finite state machine; model-based testing; Process control; register transfer level; Registers; Software; Software reliability; Timing; timing sequence
• ISSN: 2767-6684
• DOI: 10.1109/DSA56465.2022.00021

To improve the reliability of the digital circuit, it is necessary to verify the Register Transfer Level (RTL) design. Model-based testing and verification methods are one of the most effective methods in the field of software engineering and have been applied to the verification of digital circuit. However, some modeling methods cannot well reflect the timing sequence of digital circuits, and some methods are limited by circuit scale and have high execution complexity. The Extended Finite State Machine (EFSM) is a common software description model, which can precisely describe the dynamic behaviors of the complex system. This paper proposes an EFSM modeling method for RTL digital circuit to describe the behaviors and timing sequence of digital circuit. Based on this EFSM model, the digital circuits can be better tested and verified. With the internal control flow analysis of the process blocks in RTL digital circuit, this paper proposes an algorithm for constructing the sub-EFSM model for the process block. Furthermore, this paper proposes an algorithm to merge sub-EFSM models based on timing sequence analysis of process blocks to build the EFSM model. Taking six RTL digital circuits as experimental subjects, constructing EFSM models and generating test cases, the results show that the method proposed in this paper can effectively construct the EFSM model of RTL digital circuit and services for automatic testing generation.