Real Time Simulation of Transient Overvoltage and Common-Mode during Line-to-Ground Fault in DC Ungrounded Systems

• Published in: IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society Vol. 1; pp. 6451 - 6456
• Main Authors: Vygoder, Mark, Gudex, Jacob, Cuzner, Robert, Milton, Matthew, Benigni, Andrea
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2019
• Subjects: Circuit faults; Engines; Fault protection; Field programmable gate arrays; Hardware-in-the loop simulation; Mathematical model; microgrids; Power distribution faults; Power electronics; Power system simulation; Real-time systems; Transient analysis
• ISSN: 2577-1647
• DOI: 10.1109/IECON.2019.8927034

Real Time (RT) simulation of Power Electronics (PE) allows engineers to interface real-time controls for controller hardware-in-the-loop CHiL. CHiL verification moves a design from Technology Readiness Level (TRL) 3 to TRL 4. For RT CHiL simulation of DC protection systems, the RT simulation platform must be able to simulate common mode behavior, various grounding schemes, and fault transients at sufficiently high resolution so as not to interfere with the protection system design. This paper demonstrates this capability using a Latency Based Linear Multistep Compount (LB-LMC) simulation method implemented in Field Programmable Gate Arrays (FPGAs), in order to achieve 50ns resolution of common mode behaviors, including Line-to-Ground (LG) overvoltages resulting from LG faults and fault recovery in ungrounded DC systems. This resolution in RT cannot be achieved with today's commercial off-the-shelf (COTS) RT CHiL platforms. Furthermore, this capability can be expanded to other grounding schemes and larger PE networks, enabling RT CHiL validation of protection schemes for networks of power electronic converters at TRL 4.