Modelling of circuits and systems using PNs with applications to test generation for VLSI circuits

• Published in: ASIC, 2003. Proceedings. 5th International Conference on Vol. 2; pp. 1155 - 1158 Vol.2
• Main Author: Kadim, H.J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• ISBN: 0780378946; 078037889X; 9780780378940; 9780780378896
• ISSN: 1523-553X
• DOI: 10.1109/ICASIC.2003.1277418

Many of the commonly used techniques for automatic test generation are based on ideas of path sensitization. Such approaches involve two stages: (1) the generation of a path that is sensitive to the presence of the fault, and (2) justification of values along the path by propagating signals back to primary inputs. Each stage requires detailed tracing through the circuit and in a number of passes and extensive backtracking may be required to resolve conflicts. The work presented in this paper demonstrates how such problems may be avoided by the use of Petri nets. Algorithms associated with such nets together with more general graph algorithms are used to obtain test patterns with high fault coverage. Each test is generated independently from the previous test, with repetition and symmetry in the circuit structure being used to obtain full coverage very rapidly.