Enhancement of RF Power Measurement in 1/f Noise Using FPGA

This paper presents a proposed architecture for enhancing RF power measurement in 1/f noise using field programmable gate array (FPGA). Algorithm development and verification is first done on Matlab. Next, Quartus II and ModelSim software is used to implement the algorithm on FPGA. A real noise sign...

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Bibliographic Details
Published in2018 2nd International Conference on Imaging, Signal Processing and Communication (ICISPC) pp. 143 - 148
Main Authors Zulkipli, Nuzulan Naim, Sha'ameri, Ahmad Zuri, Aspar, Zulfakar, Hussin, Ghazali
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2018
Subjects
1/f noise
Computer architecture
Correlation
Field programmable gate arrays
FPGA
Noise reduction
power estimation
Power measurement
Radio frequency
RF power
wavelet
Wavelet transforms
whitening
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DOI10.1109/ICISPC44900.2018.9006683

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Summary:This paper presents a proposed architecture for enhancing RF power measurement in 1/f noise using field programmable gate array (FPGA). Algorithm development and verification is first done on Matlab. Next, Quartus II and ModelSim software is used to implement the algorithm on FPGA. A real noise signal from industrial collaborator is used to verify the performance and functionality of the implementation. The proposed architecture consists of five main modules which are whitening, wavelet decomposition, denoising, signal recovery and power estimation. Based on the implementation result, the proposed architecture shows 1.74 % percentage of error at 10 dBm signal power and 60.85 dB SNR and utilized 2.84 % logic elements (LE).
DOI:10.1109/ICISPC44900.2018.9006683