Interface engineering for highly-reliable 65 nm-node Cu/ULK (k=2.6) interconnect integration

• Published in: Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005 pp. 21 - 23
• Main Authors: Ishii, A., Matsumoto, S., Hattori, T., Suzuki, S., Isono, S., Iwasaki, A., Tomita, K., Hashimoto, K., Tawa, S., Furusawa, T., Kodama, D., Ogawa, S., Suzumura, S., Tsutsue, M., Goto, K., Kobayashi, K., Ohshita, H., Hamada, M., Amoh, N., Okamura, H., Yonekura, K., Hamatani, T., Kobayshi, T., Tsukamoto, K., Matsuura, M.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 30.08.2005
• Subjects: Degradation; Dielectrics; Geometry; Large scale integration; Manufacturing industries; Manufacturing processes; Reliability engineering; Semiconductor device manufacture; Testing; Ultra large scale integration
• ISBN: 078038752X; 9780780387522
• ISSN: 2380-632X
• DOI: 10.1109/IITC.2005.1499910

Interface engineering technologies are developed for highly-reliable 65 nm-node Cu/low-k interconnect integration using a ULK dielectric (k=2.6) in a hybrid ILD structure. For electromigration (EM) reliability, the mechanical integrity at the SiOC/SiC(N,O) interface exposed on the via sidewalls is found to be critical. For TDDB reliability, reduction in Cu-containing defects at the SiC(N,O)/SiOC interface at the top of the metal line is critical. By optimizing these interfaces, the EM and the TDDB lifetimes are significantly improved.