An LMS-based Calibration Technique Using On-chip PN Signal for SAR ADCs

This paper introduces a calibration technique for capacitor mismatches in a Successive Approximation Register (SAR) ADC, based on the Least Mean Square (LMS) algorithm. The Capacitor Digital-to-analog Converter (CDAC) in a SAR ADC is reused and driven by a Pseudo-Random (PN) sequence generator, gene...

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Bibliographic Details
Published in2024 6th International Conference on Circuits and Systems (ICCS) pp. 124 - 128
Main Authors Zheng, Chengye, Sun, Jie, Wang, Chenghua
Format Conference Proceeding
LanguageEnglish
Published IEEE 20.09.2024
Subjects
Accuracy
Calibration
Capacitors
digital Calibration
dynamic Iteration Step
Dynamic range
Generators
Hardware
Heuristic algorithms
LMS
PN-generator
Registers
SAR ADC
Signal generators
System-on-chip
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DOI10.1109/ICCS62517.2024.10846770

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Summary:This paper introduces a calibration technique for capacitor mismatches in a Successive Approximation Register (SAR) ADC, based on the Least Mean Square (LMS) algorithm. The Capacitor Digital-to-analog Converter (CDAC) in a SAR ADC is reused and driven by a Pseudo-Random (PN) sequence generator, generating on-chip analog input signals for LMS calibration. A dynamic iteration step size is implemented to increase convergence speed and accuracy. The calibration circuit does not sacrifice the conversion speed or significantly increase the hardware as traditional LMS-based calibration techniques. The calibration technique is verified based on a 14-bit SAR ADC model. Compared with the results before calibration, this work improve the Spurious Free Dynamic Range (SFDR) performance from 63.4dbc to 106.5dbc. Additionally, the Integral Nonlinearity (INL) performance improved from 50LSBs to 2LSBs.
DOI:10.1109/ICCS62517.2024.10846770