Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms

As the depth of DNN increases, the need for DNN calculations for the storage and computing power of the underlying computing platform is increasing. In this work, we implement an accelerator on FPGA for deep learning algorithms (CNN and RNN). The core computing module of the accelerator is a 32 * 32...

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Bibliographic Details
Published inLecture notes in computer science Vol. 11276; pp. 153 - 158
Main Authors Yang, Zhijie, Wang, Lei, Ding, Dong, Zhang, Xiangyu, Deng, Yu, Li, Shiming, Dou, Qiang
Format Book Chapter
LanguageEnglish
Published Switzerland Springer International Publishing AG 01.01.2018
Springer International Publishing
SeriesLecture Notes in Computer Science
Subjects
Accelerator
Data mapping
DNN
Systolic array
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ISBN9783030056766
3030056767
ISSN0302-9743
1611-3349
1611-3349
DOI10.1007/978-3-030-05677-3_16

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Summary:As the depth of DNN increases, the need for DNN calculations for the storage and computing power of the underlying computing platform is increasing. In this work, we implement an accelerator on FPGA for deep learning algorithms (CNN and RNN). The core computing module of the accelerator is a 32 * 32 systolic array of PEs. A mapping method for variable size of CNN and RNN algorithms is proposed. The experiment result shows that the maximum power consumption of the accelerator is 7.5W@100Mhz, the peak performance is 0.2Tops/s, and the real performance is 7.6Mops@100Mhz when running the 1st layer of LeNet-5.
ISBN:9783030056766
3030056767
ISSN:0302-9743
1611-3349
1611-3349
DOI:10.1007/978-3-030-05677-3_16