An innovative timing slack monitor for variation tolerant circuits

To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure...

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Bibliographic Details
Published in2009 IEEE International Conference on IC Design and Technology pp. 215 - 218
Main Authors Rebaud, B., Belleville, M., Beigne, E., Robert, M., Maurine, P., Azemard, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
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ISBN1424429331
9781424429332
ISSN2381-3555
DOI10.1109/ICICDT.2009.5166299

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Summary:To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure, coupled with a specific detection window generation, embedded within the clock-tree, can anticipate timing violations to prevent system failures in real-time. Performances simulated in a 45 nm technology demonstrate a scalable, low power and low area cell which can be easily inserted in a standard CAD flow.
ISBN:1424429331
9781424429332
ISSN:2381-3555
DOI:10.1109/ICICDT.2009.5166299